`timescale 1ns/1ps
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// *********************************************************************************
// Project Name : 
// Author       : Dark
// Create Time  : 2023-02-04 09:31:09
// Revise Time	: 2023-02-04 09:31:09
// File Name    : alu_src.sv
// Abstract     :
`include "defines.svh"
module alu_src(
	input	logic			alu_srcA,	//alu operand select signal A
	input	logic	[ 1:0]	alu_srcB,	//alu operand select signal B
	input	logic	[31:0]	PC,	
	input	logic	[31:0]	imm,
	input	logic	[31:0]	rs1_data,	
	input	logic	[31:0]	rs2_data,	

	output	logic	[31:0]	operand_A,
	output	logic	[31:0]	operand_B
	);

//=================================================================================
// Signals
//=================================================================================

//=================================================================================
// Body
//=================================================================================

	// operand A mux2
	assign 	operand_A 	= (alu_srcA == `A_RS1) ? rs1_data : PC;
	// operand B mux3
	always_comb begin
	    case(alu_srcB)
	        `B_RS2	 		: operand_B = rs2_data;
	        `B_IMM	 		: operand_B = imm;
	        `B_4BYTE 		: operand_B = 32'd4;
	        default  		: operand_B = 32'd0;
	    endcase
	end

endmodule
